1. Field of the Invention
The present invention relates to a semiconductor memory device and, for example, a semiconductor memory device having static memory cells.
2. Description of the Related Art
Along with the advance in the micropatterning technology for semiconductor elements and the improvement of the performance of semiconductor integrated circuits, high power consumption is becoming a serious problem for recent semiconductor integrated circuits. To solve this problem, a technique of dynamically controlling the operating frequency and power supply voltage in accordance with the load of a data process is employed. More specifically, in a low-load process, power consumption is suppressed by lowering the power supply voltage and operating frequency. To reduce power consumption of a semiconductor integrated circuit by such control, it is important to minimize the operating voltage in the low-load process.
However, in an SRAM (Static Random Access Memory) that is often used as a semiconductor memory in a semiconductor integrated circuit, the voltage margin of a memory cell decreases to make it difficult to execute a low-voltage operation as the device scaling progresses. When an SRAM operates at a low voltage, the static noise margin (SNM) and write margin (WM) representing the characteristic of a memory cell deteriorate, or the cell current decreases.
In a related technique of this kind, the power supply voltage of a memory cell is controlled in accordance with the magnitude of the threshold voltage of a transistor in a static memory cell (Jpn. Pat. Appln. KOKAI Publication No. 2004-5777).